ULSI Process Integration III: Proceedings of the International Symposium

achieved active addition annealing applications barrier body bulk capacitance capacitor cell channel characteristics charge circuit CMOS compared concentration conventional crystal defect density dependence deposition developed devices dielectric diffusion discussed distribution doping drain DRAM effect electrical Electron energy etching fabrication Figure film flow followed formation formed frequency gate higher hole IEEE implantation important improved increase integration interconnect interface introduced isolation junction layer leakage length limited lithography lower material measured memory metal mobility MOSFET needed nitride node obtained operation oxide parameters particles performance Phys poly potential present production reduced region reliability removal reported resistance scaling semiconductor shift shown in Fig shows SiGe silicon simulation single SiO2 step stress structure substrate surface techniques temperature thermal thickness thin threshold voltage transistor trench values voltage wafer