Low Power Design in Deep Submicron ElectronicsW. Nebel, Jean Mermet Springer Science & Business Media, 30 июн. 1997 г. - Всего страниц: 580 Decreasing power dissipation per logic function has become a primary concern in virtually all CMOS system chips designed today as a result of the relentless progress in processing technology that has led us into the deep-submicron age. Evolution from 1 micron to 0.1 micron lithography in the next decade will not be possible without a change in the way we design CMOS systems. But power reduction requires an overall optimisation, ranging from software compilation over instruction set design down to the introduction of much more parallelism in the architecture, the optimal use of memory hierarchy, new clocking strategies, use of asynchronous techniques, new CMOS circuit techniques and management of leakage currents in new low power technologies. Moreover, performance and power dissipation will come to be dominated by interconnect and thus completely new floor planning and place and route strategies are emerging. The chapters in this book present a systematic coverage of deep submicron CMOS digital system design for low power, from process technology all the way up to software design and embedded software systems. Audience: An excellent guide for the practising engineer, researcher and student interested in this crucial aspect of actual CMOS design. |
Содержание
I | 1 |
II | 9 |
III | 45 |
IV | 79 |
V | 81 |
VI | 105 |
VII | 135 |
VIII | 179 |
XIII | 357 |
XIV | 381 |
XV | 395 |
XVI | 397 |
XVII | 419 |
XVIII | 433 |
XIX | 461 |
XX | 493 |
Другие издания - Просмотреть все
Low Power Design in Deep Submicron Electronics Wolfgang Nebel,Jean Mermet Недоступно для просмотра - 2014 |
Часто встречающиеся слова и выражения
ACM/IEEE algorithm application approach architecture asynchronous battery Boolean cache capacitor cell chip clock cycle clock tree CMOS CMOS Circuits computed Computer-Aided Design constraints correlations cost delay model Design Automation Conf Design Automation Conference devices driver dynamic Electronics Elmore delay encoding energy executed factor fanout finite state machine frequency function glitches IEEE implementation increase instruction interconnect latch layout leakage load logic synthesis Low Power Design low-power macro-modeling memory merging microprocessor minimize minimum modules MOSFETs node operation optimization output parallel Pedram performance pipeline power consumption power dissipation power estimation power management primary inputs problem Proc processor reduced RISC routing sequential sequential circuits shown in Figure signal probabilities simulation skew solution speed static superscalar supply voltage switched capacitance switching activity techniques threshold voltage tion transistor transition variables vector VLSI wire wiresizing