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alloyed analog circuits annealing applications barrier barrier metal BSTSOI capacitance capacitor cell characteristics charge pumping chip CMOS crystal defect density deposition dielectric diffusion dopant doping drain DRAM effect electrical Electrochem Electron Devices epitaxial etch rate fabrication Figure FinFETs Flash frequency gate dielectric gate electrode gate length gate oxide gate stack germanium hole Holonyak IEDM Tech IEEE Trans implantation improved increase Integrated Circuit interconnect interface layer leakage current low-k mask material measured metal mobility MOSFET n-channel n-type nitride NMOS optimized oxide thickness p-n junction p-n-p transistor parameters particles PDSOI performance Phys planar plasma PMOS poly poly-Si polysilicon Proc reduced region reliability resistance roadmap scaling SDOI semiconductor SGOI shown in Fig shows Si-Fins SiGe silicide simulation SixGei.x strained-Si stress structure substrate surface TDDB techniques technology node temperature thermal thin threshold voltage transconductance transistor trench tunnel oxide ULSI VLSI wafer width
Стр. 388 - L. Manchanda, ML Green, RB van Dover, MD Morris, A. Kerber, Y. Hu, J.-P. Han, PJ Silverman, TW Sorsch, G. Weber, V. Donnelly, K. Pelhos, F. Klemens, NA Ciampa, A. Kornblit, YO Kim, JE Bower, D. Barr, E. Ferry, D. Jacobson, J. Eng, B. Busch, and H. Schulte, "Si-doped aluminates for high temperature metal-gate CMOS: Zr-Al-Si-O, a Novel gate dielectric for low power applications,
Стр. 503 - SON process , the silicon film and buried insulator, both of nanometric scale, are defined by epitaxy on a bulk substrate. Therefore, the SON process opens access to extremely thin films (the Silicon channel as well as the BOX) at the same time offering the thickness control as fine as the resolution of the epi process (less than Inm).
Стр. 205 - A Stochastic Wire-Length Distribution for Gigascale Integration (GSI) - Part I: Derivation and Validation", IEEE Trans.
Стр. 39 - With the advent of the transistor and the work in semiconductors generally, it seems now possible to envisage electronic equipment in a solid block with no connecting wires. The block may consist of layers of insulating, conducting, rectifying and amplifying materials, the electrical functions being connected directly by cutting out areas of the various layers.
Стр. 62 - EH Snow, AS Grove, BE Deal, and CT Sah, "Ion Transport Phenomena in Insulating Films,
Стр. 66 - JR Brews, W. Fichtner, EH Nicollian, and SM Sze, "Generalized guide for MOSFET miniaturization," IEEE Electron Device Lett., vol.
Стр. 67 - GD Wilk, RM Wallace, and JM Anthony, "High-k gate dielectrics: Current status and materials properties considerations", J.
Стр. 236 - Y. Taur, DA Buchanan, W. Chen, DJ Frank, KE Ismail, SH Lo, GA Sai-Halasz, RG Viswanathan. HJC Wann, SJ Wind, and HS Wong, "CMOS scaling into the nanometer regime,
Стр. 56 - W. Shockley, GL Pearson, and JR Haynes, "Hole Injection in Germanium — Quantitative Studies and Filamentary Transistors,
Стр. 17 - I reasoned that polycrystalline germanium, with its variations in resistivity and its randomly occurring grain boundaries, twins and crystal defects that acted as uncontrolled resistances, electron or hole emitters and traps would affect transistor operation in uncontrolled ways.