The SPARC Architecture Manual: Version 9PTR Prentice Hall, 1994 - Всего страниц: 357 SPARC (Scalable Processor Architecture) is the industry's only openly defined and evolved RISC architecture. Version 9 is the new 64-bit incarnation of SPARC - the most significant change since SPARC's introduction in 1987! Unlike other RISC (Reduced Instruction Set Computer) designs, SPARC specifies not a hardware implementation ("chip"), but an open, standard architecture belonging to the community of SPARC vendors and users. The SPARC specification is defined by the SPARC Architecture Committee, a technical arm of the computer-maker consortium, SPARC International. Version 9 provides 64-bit data and addressing, support for fault tolerance, fast context switching, support for advanced compiler optimizations, efficient design for Superscalar processors, and a clean structure for modern operating systems. The V9 architecture supplements, rather than replaces, the 32-bit Version 8 architecture. The non-privileged features of Version 9 are upward-compatible from Version 8, so 32-bit application software can execute natively, without modification, on Version 9 systems - no special "compatibility mode" is required. Publication of the Version 9 architecture marks a three-year development effort by SPARC International member companies from a broad cross-section of disciplines. |
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B | 2 |
Definitions | 9 |
Architectural Overview | 15 |
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Часто встречающиеся слова и выражения
address space aligned allows alternate space annul Appendix architecture Assembly Language Syntax atomic bits Branch byte cache CALL cause changes compatibility complete condition codes contains contents defined delay dependent described Description double doubleword effective address Equal example exception execution field Figure floating-point register FLUSH Format fre&rd fregrs2 global hardware impl implementation implementation-dependent indicates instruction integer interrupt issued label Less load load/store MAXTL MEMBAR memory model mode modify Move multiply normal occurs Opcode operand operations OTHERWIN overflow performed Precise prefetch privileged processor Programming Note r[rd rd op3 rs1 RED_state references register windows regrd regrsl require reset RESTORE result SAVE sequential consistency signed SPARC SPARC-V9 specified spill Suggested Assembly Language taken tion transfer trap trap handler trap type Unsigned write written zero
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