Low-Voltage CMOS Log Companding Analog DesignSpringer Science & Business Media, 30 июн. 2003 г. - Всего страниц: 192 Low-Voltage CMOS Log Companding Analog Design presents in detail state-of-the-art analog circuit techniques for the very low-voltage and low-power design of systems-on-chip in CMOS technologies. The proposed strategy is mainly based on two bases: the Instantaneous Log Companding Theory, and the MOSFET operating in the subthreshold region. The former allows inner compression of the voltage dynamic-range for very low-voltage operation, while the latter is compatible with CMOS technologies and suitable for low-power circuits. The required background on the specific modeling of the MOS transistor for Companding is supplied at the beginning. Following this general approach, a complete set of CMOS basic building blocks is proposed and analyzed for a wide variety of analog signal processing. In particular, the covered areas include: amplification and AGC, arbitrary filtering, PTAT generation, and pulse duration modulation (PDM). For each topic, several case studies are considered to illustrate the design methodology. Also, integrated examples in 1.2um and 0.35um CMOS technologies are reported to verify the good agreement between design equations and experimental data. The resulting analog circuit topologies exhibit very low-voltage (i.e. 1V) and low-power (few tenths of uA) capabilities. Apart from these specific design examples, a real industrial application in the field of hearing aids is also presented as the main demonstrator of all the proposed basic building blocks. This system-on-chip exhibits true 1V operation, high flexibility through digital programmability and very low-power consumption (about 300uA including the Class-D amplifier). As a result, the reported ASIC can meet the specifications of a complete family of common hearing aid models. In conclusion, this book is addressed to both industry ASIC designers who can apply its contents to the synthesis of very low-power systems-on-chip in standard CMOS technologies, as well as to the teachers of modern circuit design in electronic engineering. |
Содержание
4 | 3 |
2 | 23 |
Summary of proposed lowvoltage basic building | 26 |
Small signal Parameters | 30 |
Technology Mismatching Model | 36 |
AMPLIFICATION AND | 51 |
4 | 79 |
15 | 95 |
PTAT GENERATION | 125 |
PULSE DURATION MODULATION | 137 |
DYNAMIC RANGE | 145 |
HEARING AIDS | 157 |
CONCLUSIONS | 177 |
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Low-Voltage CMOS Log Companding Analog Design Francisco Serra-Graells,Adoración Rueda,José L. Huertas Ограниченный просмотр - 2006 |
Low-Voltage CMOS Log Companding Analog Design Francisco Serra-Graells,Adoración Rueda,José L. Huertas Недоступно для просмотра - 2013 |
Low-Voltage CMOS Log Companding Analog Design Francisco Serra-Graells,Adoración Rueda,José L. Huertas Недоступно для просмотра - 2003 |
Часто встречающиеся слова и выражения
all-MOS amplifier analog circuit Analog Integrated Circuits basic building blocks biasing BiCMOS C.C.Enz C.Toumazou capacitance capacitor cell Chapter Charge Pump Circuits and Signal Circuits and Systems Circuits and Systems-II Class AB Class-A CMOS implementations CMOS process CMOS technologies companding function Companding Theory compression compressor and expander computed current mirror Current-Mode D.R.Frey depicted in Figure domain drain current dynamic range equation equivalent frequency frequency compensation Hearing Aids I/V curves IEE Electronics Letters IEEE Journal IEEE Transactions International Symposium inversion region J.Mulder Journal of Analog Journal of Solid Kluwer Academic Publishers Log companding Log-Domain Filters Low-Power low-voltage CMOS MOS devices MOS transistors MOSFET NMOS noise non-linear operating point Operational Amplifier output parameters PTAT ratio regions of operation resistor resulting Signal Processing simulation Solid State Circuits specific strategy strong inversion Symposium on Circuits synthesis system-on-chip topologies Transactions on Circuits transconductance transfer function Translinear tuning V-domain W.A.Serdijn